Free Access
Genet. Sel. Evol.
Volume 38, Number 3, May-June 2006
Page(s) 265 - 279
Published online 26 April 2006
Genet. Sel. Evol. 38 (2006) 265-279
DOI: 10.1051/gse:2006003

Parallel computations on pedigree data through mapping to configurable computing devices

John M. Henshall and Bryce Alvin Little

FD McMaster Laboratory Chiswick, CSIRO Livestock Industries, Armidale, New South Wales 2350, Australia

(Received 16 August 2005; accepted 18 November 2005; published online 26 April 2006)

Abstract - Pedigree data structures have a number of applications in genetics, including the estimation of allelic or haplotype probabilities in humans and agricultural species, and the estimation of breeding values in agricultural species. Sequential algorithms for general purpose CPU-based computers are commonly used, but are inadequate for some tasks on large data sets. We show that pedigree data can be directly represented on Field Programmable Gate Arrays (FPGA), allowing highly efficient massively parallel simulation of the flow of genes. Operating on the whole pedigree in parallel, the transmission of genes can occur for all individuals in a single clock cycle. By using FPGA, the algorithms to estimate inbreeding coefficients and allelic probabilities are shown to operate hundreds to thousands of times faster than the corresponding sequentially based algorithms. Where problems can be largely represented in an integer form, FPGA provide an efficient platform for computations on pedigree data.

Key words: FPGA / parallel computations / pedigree data

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© INRA, EDP Sciences 2006